PWM0_SM0=0, UART3=0, UART1=0, CMP=0, UART2=0, UART0=0, I2C0=0, EWM=0, PWM0_SM2=0, PWM0_SM3=0, PWM0_SM1=0
System Clock Gating Control Register 4
| EWM | EWM Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C0 | I2C0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C1 | I2C1 Clock Gate Control |
| UART0 | UART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART1 | UART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART2 | UART2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART3 | UART3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CMP | Comparators Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PWM0_SM0 | PWM0 submodule 0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PWM0_SM1 | PWM0 submodule 1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PWM0_SM2 | PWM0 submodule 2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PWM0_SM3 | PWM0 submodule 3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |